The present invention relates to a semiconductor integrated circuit (IC). More particularly, the present invention pertains to a technique which may be effectively employed in an input/output buffer of a gate array IC which is one type of semi-custom IC.
A gate array IC includes an internal circuit section in which a multiplicity of basic cells are arranged, and a multiplicity of buffer sections disposed around the internal circuit section.
Each basic cell is composed of circuit elements required to constitute a basic logic circuit, e.g., an MOS field-effect transistor and a resistor, which are formed in a semiconductor substrate. Provision of a multiplicity of such basic cells enables various kinds of circuits or systems to be formed relatively readily and at reduced costs in accordance with the orders placed by individual customers simply by changing wiring patterns.
Each buffer section is composed of a pair of circuit elements, one of them constituting an input buffer circuit, and the other constituting an output buffer circuit. Either the input or output buffer circuit is selectively formed in accordance with the type of circuit of system formed in the internal circuit section.
Hitachi Ltd. has already developed a Bi-CMOS gate array IC capable of effecting high-speed signal processing at reduced power consumption. In this gate array IC, a complex switching circuit of a CMOS element and a bipolar element is employed, such as that shown in, e.g., A. Uragami et al--U.S. patent application Ser. No. 704,209.
The present inventors made various efforts to improve the performance of this Bi-CMOS gate array IC and have discovered the following points.
The buffer section has a signal voltage level converting function for converting a TTL (Transistor Transistor Logic) or ECL (Emitter Coupled Logic) level signal to a CMOS level signal. This input/output buffer circuit is basically designed to serve as an inverter circuit, and no consideration has heretofore been taken to arranging the input/output buffer so that it can form other kinds of logic circuits in accordance with the input conditions of an input signal.
It is often experienced that the waveform of a signal input to a gate array IC is distorted by transmission through a relatively long communication line. It has also been found that various kinds of noise are superposed on the input signal. The present inventors have revealed that, when such an input signal is received, it is necessary to employ, as an input buffer circuit, a circuit which has a wave-shaping function and which is not easily affected by any noise, such as a Schmitt trigger circuit.
In addition, there are cases when it is desired not only to invert an input signal and transmit the inverted signal to an internal logic but also to obtain a signal which is in phase with an input signal, as an input buffer output. In such a case, the inventors determined, prior to accomplishing the present invention, that an inverter circuit which is formed by employing a basic cell in the internal circuit section can be connected to the output end of an inverter type input buffer circuit, thereby obtaining an in-phase output. This arrangement, however, reduces the number of basic cells which can be used in the internal circuit section. The present inventors have also found that, when an input buffer section and an internal circuit section are spaced apart from each other by a relatively long distance, the delay in transmission of an input signal between two inverter circuits becomes undesirably large. Thus, the restriction on the kinds of available input buffer circuits is one of the primary causes which limit the range within which the gate array IC can be used. The above matters have been clarified by the inventors through their studies.